A Modular Reconfigurable Architecture for Efficient Fault Simulation in Digital Circuits

In this paper, we describe a modular reconfigurable architecture for efficient stuck-at fault simulation in digital circuits. The architecture is based on a Universal Faulty Gate Block, which models each 2-input gate by a 4-input Look-Up Table (LUT) and a Shift-Register (SR) with 3 stages, and relies on colapsing the stuck-at fault list of the gates using equivalence and dominance relations between faults. An example is presented, the expected performance is estimated and the applicability and limitations of the architecture are discussed.